As the semiconductor design and the manufacture technique update, the rate of improvement in components accelerates, and the size of panel and the resolution of TFT-LCD increase, the distortion of the gate pulse signal due to the resistance-capacitance (RC) signal delays will increase. To decrease the RC signal delays, low resistance material for the connection between the components must be chosen. As the density of the components increases, the line width of the connection will decrease to induce the electromigration problems by high current density, so that it becomes a factor in choosing the material. Generally speaking, the conventional connection material is aluminum (Al) which resistivity is about 2.66 μΩ-cm. But using copper (1.67 μΩ-cm) or silver instead of aluminum for connection material is regarded as a practicable proposal gradually because copper and silver have higher resistance-to-electromigration and lower resistivity than aluminum.
Referring to FIG. 1, a schematic view of a conventional thin film transistor is illustrated. The conventional thin film transistor comprises a substrate 11, a gate electrode 12, a gate insulating layer 13, a semiconductor layer 14, a source electrode 15, and a drain electrode 16. A gate metal is sputtered by physical vapor deposition (PVD) on the substrate 11. After patterning the gate metal by a first photolithography process to form the gate electrode 12, the gate insulating layer 13 and the semiconductor layer 14 are then sequentially deposited on the substrate 11 by Plasma Enhanced Chemical Vapor Deposition (PECVD) and patterned by a second photolithography process, wherein the gate insulating layer 13 can be a SiNx or SiOx. Then, a second metal layer (source/drain) is sputtered and patterned by a third photolithography process to form the source electrode 15 and the drain electrode 16, wherein the source electrode 15 and the drain electrode 16 are separated by a channel region by etching. Furthermore, the conventional thin film transistor could further comprise a passivation layer and an indium-tin-oxide (ITO) layer which are then patterned by a fourth and a fifth photolithography process, respectively. As manufacturing technique varies, there are four to six steps of photolithography processes in application. This prior art is focused on the structure of the conventional thin film transistor for gist description and is ignored about the other details and principles.
However, in conventional thin film transistor which uses copper to be a gate electrode that at least has following disadvantages. For example, before using PECVD to form the gate insulating layer 13, copper usually suffers oxidation that produces bubbles by reacting with other materials and produces an internal reaction in PECVD and ammonia. The cupric oxide may increase the resistance. In addition, copper expands to silicon easily, for example, the substrate 11 which the principle is silicon, the gate insulating layer 13, and the semiconductor layer 14 having amorphous silicon that become a CuSix layer through the reaction that causes instability in the thin film transistor. Moreover, the adhesion in copper and the substrate 11 is bad that causes the peeling of the gate insulating layer 12 after forming gate electrode. The yield of thin film transistor is also decreased due to the characteristic as mentioned above. In order to manufacture thin film transistor, providing better adhesion characteristic and low resistance are a key factor that research and development (R&D) staffs must solve instantly.